1. Field of the Invention
The present invention relates to the field of data caching within computer systems and more particularly to the field of projected cache structures used to evaluate performance of a cache.
2. Description of Related Art
Cache memory is widely employed in contemporary computer systems. Cache memory is a type of fast-access memory that is typically used to buffer certain information for rapid access that is permanently stored in slower-access memory, such as a magnetic disk or other direct access storage device (DASD). Since cache memory can be substantially more expensive than magnetic disk storage having the same storage capacity, most computer systems have a relatively limited amount of cache memory.
To maximize the efficient use of cache memory, most systems implement a caching strategy that manages the type of data stored in the cache memory and the format in which the data is stored. One commonly employed caching strategy is a least-recently-used (LRU) replacement strategy in which a double-linked list of cache entries is created to identify the data content stored in the cache. This LRU cache list may contain multiple entries that are arranged in order of how recently a data set has been requested by a user or application. At the beginning of the list is the most recently used (MRU) entry. At the end of the list is the least recently used (LRU) entry.
Each time data is requested by a user or application, the system determines if the requested data is stored in the cache. A variety of ways exist to perform full or partial reviews of the cached data. If the requested data is stored and located in the cache memory, the system returns a cache hit and makes the requested data available. The cache list entry corresponding to the requested data may be repositioned at the MRU location. The remaining cache list entries are sequentially demoted. If the requested data is not located or found in the cache memory, the system returns a cache miss, retrieves the requested data in the DASD or other memory, and copies the requested data to the cache list. The retrieved data is generally copied to the MRU location of the cache list and the remaining cache list entries are demoted, with the LRU entry being pushed out of the LRU directory list.
One goal of cache management systems is to implement a caching strategy that maintains a high hit ratio and a corresponding low average data access time for data requests. However, currently no mechanism or process exists that is capable of determining how simulating a projected cache size, different from an actual cache size, might affect the cache performance for a given system. Currently, in order to determine how a different cache size might impact the performance of a cache subsystem or a computer system, the actual cache size must be physically altered either by removing existing cache or adding additional cache.
The prior art does set forth limited proposals that may impact the performance of a given cache, but nothing addresses the performance of a projected cache size. One method set forth in the prior art is to allocate certain portions of actual cache memory to multiple applications that are requesting data at approximately the same time. This implementation addresses the performance of an installed cache, but does not reach the potential impact of a projected cache size.
The prior art also discusses employing a cache arbiter that monitors the cache demands and balances such demands with other demands for processor storage. The arbiter dynamically alters the size of cache available to a given application through the utilization of expanded storage resources. The objective of this method is to dynamically utilize expanded storage resources in order to maximize the system throughput. Nevertheless, this implementation does not address the potential impact on cache performance of a projected cache size.
The prior art further addresses the possibility of implementing cache statistics in order to predict cache hit rates and determine the best data candidates for caching. Still further, the prior art sets forth a method for compressing some or all of the data stored in cache memory in order to make additional cache resources available for storing additional data content. Once again, while these prior art conceptions attempt to address the performance of actual cache memory in a computer system, they do not reach the potential performance impact of a projected cache size.
Consequently, what is needed is a process, apparatus, and system that are configured to monitor cache performance statistics, such as cache hit ratios and average access times, associated with a projected cache size without the space overhead of a physically larger cache. Beneficially, such a process, apparatus, and system would be further configured to compare projected performance parameters to actual performance parameters and communicate an optimization parameter to a user or administrator application.